Digital to analog converts are well known in the art. They function to convert a digital input code to an output analog entity, typically voltage or current. One challenge in the design of a DAC is the filtering of signal images at the harmonics of the sampling frequency (fS). For the zero-order hold DAC, Sinc response of the zero-order hold function filters the desired signal. As the signal bandwidth increases given a sampling frequency, the desired roll-off is far from achievable using the Sinc response. Oversampling is one technique used to distance the images in the frequency domain. But as the signal bandwidth increases, oversampling by a higher factor increases the overall complexity of the system while still being unable to achieve the desired roll-off for wide-band signals.
A diagram illustrating an example output of a prior art zero-order hold DAC in time and frequency is shown in FIG. 1. Where x(t) 10 in the upper graph represents the desired signal in the time domain and xq(t) 12 represents the quantized signal. In the lower graph, dashed line 14 represents the desired signal while dashed lines 18 represent images in the frequency domain.
Linear interpolation between the input samples can be applied for a better roll-off achieving a Sinc2 response for filtering the desired signal. It yields better performance than zero-order hold but it is still short of the desired filtering in contrast to the use of large oversampling ratios for a given scenario. Implementing oversampling at higher signal bandwidths remains a challenge although a current-based DAC approach can be used largely for modest bandwidth and oversampling frequencies. MOS currents are added based on the binary code that activates the respective MOS transistors. This technique has disadvantages and known solutions improve performance only marginally.
Digital solutions are known that use Cubic Lagrangian Interpolation between the samples followed by Cascaded integrator-comb (CIC) filters to provide filtering of the desired signal. The disadvantage of the pure digital implementation is use of adders and multipliers to implement the interpolation function that consume a lot of power and area depending upon the implementation. Moreover, to add programmability to the design requires enhanced digital structures that are typically very power hungry. The cubic interpolators and the CIC filters pose design challenges as the frequencies upscale and are limited in performance.
There is thus a need for a DAC that overcomes the problems of the prior art and that provides superior desired output performance.